Device performance in integrated circuits can be dramatically affected by extreme corners: extremes in temperature, operating voltage, and wafer processing. For certain combinations of these extreme corners, degraded device performance can cause difficulty writing the bitcells of memory arrays .e.g. SRAM's, DRAM's. For at least some of these extreme corners, bitcell writing can still be successfully achieved if sufficient time is allowed for that operation. However, building into control circuitry a longer amount of time to perform writes can also limit the performance of the memory at other corners.
In mobile applications, for example, the operating voltage may be decreased during periods of inactivity to save battery power. This low voltage combined with low temperature and the process variation of PFETs being much stronger than the NFETs, causes the bit cell write time to increase dramatically. For instance, in this type of scenario the timing column may slow down by a factor of five while the bitcells may slow down by a factor of ten, causing the write to fail. In one prior approach to the problem a fixed delay is introduced to provide a period of time for the write to be completed. Since bitcells don't respond to process variations in the same way as the timing chain or delay circuits at extreme corners, the introduced delay is not sufficient and the operation terminates before the write actually occurs. Another approach is to use the same delay produced by a read timing column (column of bitcells mimicking a standard bitcell column) for the read operation to time the write operation. There are two problems with this. First, since the read operation is normally longer than the write operation, time is wasted in the write operation. Second, in extreme comer conditions, the write can be slower than the read and the write operation is cut off before the write is complete.